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ATmega128
Table 68. Clock Select Bit Description
CS22
1
1
1
1
CS21
0
0
1
1
CS20
0
1
0
1
Description
clk I/O /256 (From prescaler)
clk I/O /1024 (From prescaler)
External clock source on T2 pin. Clock on falling edge
External clock source on T2 pin. Clock on rising edge
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Timer/Counter
Register – TCNT2
Bit
7
6
5
4
3
2
1
0
TCNT2[7:0]
TCNT2
Read/ W rite
Initial Value
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. W riting to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2 Register.
Output Compare
Register – OCR2
Bit
7
6
5
4
3
2
1
0
OCR2[7:0]
OCR2
Read/ W rite
Initial Value
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC2 pin.
Timer/Counter
Interrupt Mask
Bit
7
6
5
4
3
2
1
0
Register – TIMSK
Read/ W rite
Initial Value
OCIE2
R/ W
0
TOIE2
R/ W
0
TICIE1
R/ W
0
OCIE1A
R/ W
0
OCIE1B
R/ W
0
TOIE1
R/ W
0
OCIE0
R/ W
0
TOIE0
R/ W
0
TIMSK
? Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
W hen the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
? Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
W hen the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
158
2467X–AVR–06/11
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